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SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced early availability of the complete, silicon-proven Cadence ® Denali ® Gen2 IP for LPDDR5/4/4X in TSMC’s ...
Attopsemi, a pioneering provider of innovative One-Time Programmable (OTP) IP solutions, today announced a significant technological leap: its proprietary I-fuse technology has achieved silicon ...
Over the past few years, we've seen the foundry business evolve from a single-horse race that TSMC effectively "won" each and every cycle to a two-way competition with Samsung. Now, GlobalFoundries is ...
Silicon-proven DesignWare PHY IP on TSMC's 7nm FinFET process includes USB, DDR, LPDDR, HBM, PCI Express, MIPI, DisplayPort, and Ethernet Successful customer tapeouts of DesignWare Logic Libraries and ...
MOUNTAIN VIEW, Calif., Oct. 29, 2019 /PRNewswire/ -- Highlights: Ultra-low power DesignWare Die-to-Die PHY IP delivers less than 1pJ/bit for optimal energy efficiency in hyperscale data centers ...
Mobile chipsets are currently produced using Samsung’s well-established 10nm FinFET process. The incoming 7nm architecture is based on new Low Power Plus (LPP) Extreme Ultra Violet (EUV) technology, ...
While Intel has been having problems with mass production of its 10nm product lines, other tech giants like AMD and Samsung are well along in their 7nm endeavors. AMD is currently sampling 7nm EPYC ...
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