Design-Reuse

Single precision floating point multiplier accumulator IP Listing

Hardware floating point can be attractive in many embedded applications where integer or fixed point algorithms produce either overflow/underflow or unacceptably long word lengths. In such cases ...
EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
New Electronics

Floating point enabled microcontrollers in embedded designs

Floating point units (fpu) can increase the range and precision of mathematical calculations or enable greater throughput in less time, making it easier to meet real time requirements. Or, by enabling ...
Design-Reuse

Xilinx ISE Design Suite 13.3 Full Custom Precision Floating-Point Support Extends Productivity for DSP Designers

New Bit and Cycle Accurate, Single, Double and Full Custom Precision Floating-Point Now Available in System Generator for DSP SAN JOSE, Calif., Nov. 1, 2011 -- Xilinx, Inc. (NASDAQ: XLNX) today ...
Ars Technica

First foray into boost matrices and higher precision floating points

I've run into a problem with my project with both the speed and accuracy with a home brew matrix class using doubles. I'm inverting a matrix and multiplying it by a ...