By EDA tools, designers can finish the design flow of very large scale integrated (VLSI) chips with billions of transistors.

With a special focus on providing a hands-on training to the interested, a five-day workshop on 'VLSI Design & IC CAD (VDIC-06)' will begin at the Deemed University from December 4.

Logic Equivalence Check, popularly known as LEC is one of the most important parts of the ASIC VLSI design. Formal verification techniques have been developed using mathematical proof rather than ...